In a liquid crystal display apparatus of an active matrix drive system, a technology for causing outputs of all gate drivers to have a high voltage (VGH) at the time of turning off a power source and for removing a charge written in a pixel electrode is used so that an image does not remain on a display surface after the power source is turned off.
However, there is a case where a liquid crystal panel that is mounted on a tablet is driven by power supplied from a battery, and a sudden power source OFF state (hereinafter referred to as panic-off) is caused by removing the battery or the like. In this manner, in a case where the supply of the power is interrupted by the panic-off, since a normal display OFF sequence is not performed, a phenomenon (common name: charge remaining) in which an image remains on a display surface occurs.
In PTL 1 and PTL 2, technologies that solve such problems are disclosed.
PTL 1 discloses a method for supplying an operation power source voltage to a gate bus drive circuit through a power source retaining circuit which is capable of retaining the power for a predetermined period of time, for detecting turning off in the case where the power source is turned off, and for simultaneously turning on all transistors connected to the gate bus for a fixed period of time immediately after the power source is turned off.
PTL 2 discloses a liquid crystal display apparatus that includes two diodes which are connected in series in one direction between a drive power source for a source driver and a ground potential, and in which a source line is connected to a connecting point of the diode. According to the liquid crystal display apparatus of PTL 2, in the case where the power source is turned off, it is possible to output a gate high signal to all gate lines, and it is possible to discharge the voltage which is accumulated in a liquid crystal layer through the diode by configuring the drive power source for the source driver to the ground potential.
Moreover, in the liquid crystal display apparatus, there is a problem that in a delay of a gate signal that is transmitted by a gate line connected to a gate electrode of a TFT arranged in each pixel, the level shift of the potential of the pixel electrode due to parasitic capacitance becomes nonuniform depending on a position of the pixel, and as a result, luminance unevenness of a display image occurs.
In order to solve the problem, there is known a technology for controlling a waveform of the gate pulse so as to be a waveform having a falling slope. For example, a gate slope type liquid crystal display apparatus using such a technology is disclosed in PTL 3.
Furthermore, PTL 4 discloses a gate slope type liquid crystal display apparatus in which a countermeasure against the panic-off is carried out. FIG. 5 is a diagram illustrating a configuration example of a liquid crystal display apparatus of PTL 4. FIG. 6 is a diagram illustrating a waveform of a signal which is input to or is output from a gate drive circuit of the liquid crystal display apparatus of PTL 4.
As illustrated in FIG. 5, the liquid crystal display apparatus of PTL 4 includes a luminance slope circuit 201, a power retaining circuit 202, a power source switching circuit 203, and a gate drive circuit 204.
The luminance slope circuit 201 changes an input gate on-state voltage Von in synchronization with an output of the gate drive circuit 204 and outputs a gate on-state voltage for the gate drive circuit as illustrated in a power source Vgon of FIG. 6.
The power retaining circuit 202 retains the power supplied by the gate on-state voltage Von for a predetermined time and is configured by using a capacitor or the like having a sufficiently large capacitance.
The power source switching circuit 203 outputs an output voltage of the luminance slope circuit 201 to the gate drive circuit 204, in the case where a voltage value of an apparatus power source Vin from a power source apparatus which is not illustrated in the drawing is higher than a predetermined voltage value, and outputs an output voltage of the power retaining circuit 202 to the gate drive circuit 204 in the case where the voltage value of the apparatus power source Vin is equal to or lower than the predetermined voltage value.
The output voltage of the power source switching circuit 203, a gate off-state voltage Voff, and a logic voltage Vcc are supplied to the gate drive circuit 204.
At the time of normal driving in which the apparatus power source Vin is normally supplied to the liquid crystal display apparatus (in the case where the apparatus power source Vin is 3.3 V), the gate drive circuit 204 sequentially outputs a pulse signal (VOUT1 to VOUTn) which is generated by synthesizing the output of the luminance slope circuit 201 and the gate off-state voltage Voff per one gate line cycle. Since the output voltage of the luminance slope circuit 201 is changed in synchronization with a fall of a gate clock signal, an output VOUTi of the gate drive circuit 204 also becomes a drive waveform of which intentionally falls in a blunt manner. Accordingly, it is possible to suppress the luminance unevenness on the display surface.
On the other hand, at the time of turning off the power source in which the apparatus power source Vin supplied to the liquid crystal display apparatus is interrupted (at a time t1 in which the apparatus power source Vin becomes 0 V), the voltage which is retained in the power retaining circuit 202 at a time t2 after the power source is turned off is supplied to the gate drive circuit 204. Therefore, the gate drive circuit 204 is non-synchronized regardless of other input signals and outputs the output of the power retaining circuit 202 to all of the output terminals of the gate drive circuit 204 (VOUT1 to VOUTn).
Accordingly, all of the thin film transistors are in an ON state in a display unit 206, and the charge which remains in the liquid crystal is quickly released, and thereby, it is possible to erase the display, and it is possible to avoid an afterimage being visible at the time of turning off the power source.